1. The Field of the Invention
The present invention relates to the processing of semiconductor substrates, such as silicon wafers, which are used in the manufacture of semiconductor devices. The present invention more specifically relates to the polishing or planarizing of the surfaces of semiconductor substrates using a process known as chemical mechanical planarization (CMP). Methods disclosed herein improve the result of CMP processes when performed on an apparatus known as a linear track polisher, or on an apparatus known as a rotational polisher.
2. The Relevant Technology
In the fabrication of integrated circuits, numerous integrated circuits are typically constructed simultaneously on a single semiconductor substrate. To reduce the cost of producing individual semiconductor devices, it has long been an objective of semiconductor manufacturers to increase the number of devices on a single substrate. For a period of time this was accomplished primarily by a continual scaling down of the geometries of individual active devices within the integrated circuits.
In the context of this document, the term xe2x80x9csemiconductor substratexe2x80x9d is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term xe2x80x9csubstratexe2x80x9d refers to any supporting structure including but not limited to the semiconductor substrates described above. A substrate may be made of silicon, gallium arsenide, silicon on sapphire (SOS), epitaxial formations, germanium, germanium silicon, diamond, silicon on insulator (SOI) material, selective implantation of oxygen (SIMOX) substrates, and/or like substrate materials. Preferably, the substrate is made of silicon which is typically single crystalline.
The scaling of active devices eventually became less profitable as the limitations of the circuit speed and maximum functional density came to depend more on the characteristics of the electrical interconnects of the devices than on the scale of the devices themselves. In addition, the aspects of silicon utilization, chip costs, and ease of flexibility of integrated circuit design were also adversely affected by electrical interconnect technology restrictions. The approaches to lifting these limitations have involved the implementation of vertical stacking or integration of devices and their associated electrical interconnections, commonly referred to as multilevel interconnect (MLI) schemes. In MLI schemes, individual conductor layers are separated by dielectric layers which are sandwiched between the conductor layers. These dielectric layers are typically oxide or nitride layers which are grown or deposited on the substrate and are known as interlevel dielectrics (ILD).
One drawback of multilevel interconnection is a loss of topological planarity. Loss of planarity results in associated problems in photolithography and etch, as well as other problems. To alleviate these problems, the substrate is planarized at various points in the process to minimize non-planar topography and its adverse effects. As additional levels are added to multilevel interconnection schemes and circuit features are scaled to sub-micron dimensions, the required degree of planarization increases. Such planarization can be performed on either the conductor or the interlevel dielectric layers to remove high topography or to remove embedded particles.
The polishing process may also involve the introduction of a chemical slurry to facilitate higher removal rates and selectivity between films of the semiconductor surface. This polishing process is often referred to as chemical mechanical planarization (CMP). The chemical slurry used in CMP contains abrasives therein to assist in the mechanical removal of the layer. When fixed abrasives are incorporated into a polishing pad in a CMP process, abrasives are not needed in the chemical slurry, and a liquid ammonium solution can be used in lieu of a slurry while dripped onto the polish pad during the polishing process.
CMP is implemented in dielectric layer planarization by growing or depositing a layer, such as oxide or nitride, on the semiconductor substrate, typically to fill in contact regions or trenches between metallization lines, and then removing the excess dielectric material using the CMP process, until a flat, smooth surface is achieved.
CMP processes have been used in the semiconductor industry for many years. A primary application of CMP processing has been the polishing of silicon substrates, such as silicon wafers, before active device fabrication. Only in recent years has the CMP process been applied to planarizing metallization layers and their inter-dielectric layers, and these new applications are the result of integrated circuit device fabrication processing scaling down to deep submicron geometries. A major hurdle to overcome in adapting CMP processes to the planarization of metallization and dielectric layers is that the typical thicknesses of the layers being planarized, and the variations in final thicknesses allowed over the entire surface area of the layers, are smaller than the critical dimensions associated with earlier semiconductor applications.
In addition to the need for tight tolerances in the planarizing of semiconductor metal and dielectric layers, there is a continuing need to reduce the amount of process time associated with the CMP material removal steps.
A type of apparatus known as a rotational polisher has been used widely in the practice of chemical mechanical planarization. The rotational polishing process involves under controlled pressure and temperature. An example of such an apparatus is the Model 372 Polisher manufactured and distributed by IPEC Westech Systems, of San Jose, Calif.
FIG. 1 shows a rotational polisher 11 having a rotatable polishing platen 12, a substrate polishing head assembly 14 and a chemical supply system 18. Platen 12 is typically covered with a replaceable, relatively soft material 16 such as polyurethane.
Substrate polishing head assembly 14 holds semiconductor substrate 10 adjacent to platen 12. Substrate polishing head assembly 14 includes a motor (not shown) for rotating the polishing head and semiconductor substrate 10. Substrate polishing head assembly 14 further includes a polishing head displacement mechanism (not shown) which moves the substrate 10 back and forth across the platen 12 as it is rotating. Substrate polishing head assembly 14 applies a controlled downward pressure to semiconductor substrate 10 to hold semiconductor substrate 10 against rotating platen 12 so that a continuous polishing surface 34 on rotating 12 platen polishes semiconductor substrate 10. Chemical supply system 18 introduces a polishing slurry (not shown) to be used as an abrasive medium between platen 12 and semiconductor substrate 10.
Chemical mechanical planarization (CMP) using a rotational polishing system is a conventional polishing process. Examples of CMP are seen in U.S. Pat. No. 4,680,893 issued on Jul. 21, 1987 to Cronkhite et al., U.S. Pat. No. 5,142,828 issued on Sep. 1, 1992 to Curry, II, and U.S. Pat. No. 5,514,245 issued on May 7, 1996 to Doan et al. The Cronkhite et al. reference teaches polishing bare silicon wafers after they have been cut from a silicon ingot. The polishing requires two similar polishing steps using two dissimilar pads and two dissimilar polishing pressures. The Curry, II reference teaches removal of a defective metallization layer by a single CMP process, followed by formation of a replacement defect-free metallization layer. The single CMP process of Curry, II uses a single polishing pad at a single pressure on the defective metallization layer to remove the same. The Doan et al. reference teaches two CMP steps for planarizing a dielectric layer on a wafer. Like the Cronkhite et al. reference, the Doan et al. reference requires two dissimilar polishing pads in two respective CMP steps. The first CMP step creates defects in the polished surface and uses a hard and low compressibility polishing pad. The defects in the polished surface are removed by a second CMP step that uses a high compressibility and low hardness polishing pad. The pressure is recommended to be the same in the two CMP steps.
Limitations of conventional rotational CMP polishing apparatus and processes are known to exist. While it is preferable to have a constant material removal rate across the entire surface of the substrate, the removal rate is inherently related to the radial position of the substrate on the platen. The removal rate is increased as the semiconductor substrate is moved radially outward relative to the polishing platen due to higher platen rotational velocity. Additionally, removal rates tend to be higher at the edge of the substrate than at the center of the substrate because the edge of the substrate is rotating at a higher speed than the center of the substrate. FIG. 2 illustrates a perspective view, not to scale, of a topology having a typical thickness profile on a semiconductor substrate 10 which is an example of that which may be realized when planarizing a semiconductor substrate using rotational polisher 11 as described above.
It is known in the art that the material removal rate realized during a CMP process can be increased by adjustments such as increasing the downward pressure of substrate polishing head assembly 14 or by increasing the rotational speeds of either substrate polishing head assembly 14 or platen 12. The adjustments, however, only accentuate the unacceptable variations in semiconductor substrate thickness described above. Furthermore, the trend towards increasing the overall size of semiconductor substrates makes it increasingly difficult to hold the necessary tolerances across the entire substrate.
Doped silicon dioxide layer materials known as phosphosilicate glass (PSG) and borophosphosilicate glass (BPSG) are used widely in the fabrication of semiconductor devices, and have been further used to provide a measure of surface planarity. Phosphorus-doped oxides are known to have numerous properties which are beneficial to the long term reliability of semiconductor devices, such as providing an improved barrier to moisture penetration, and acting as an effective trap for mobile ionic contaminants. In addition, PSG and BPSG materials have been used to achieve a measure of substrate surface planarity by depositing a PSG or BPSG layer on a substrate surface, then heating the substrate to flow the glass and planarize the layer. Such a technique is commonly referred to as reflow and has proven useful in the fabrication of semiconductor devices with relatively large geometries. BPSG films reduce reflow temperatures in such processes because boron plays a principal role in the lowering of glass viscosity.
Limitations to the use of PSG and BPSG reflow are known to exist, particularly when fabricating semiconductors which have relatively small device geometries or which have three or more dielectric/metal layers. The total thermal budget available to the reflow processes for such devices has to be minimized. Consequently, in order to produce the same degree of planarization obtained in higher temperature processes, the dopant concentration in the BPSG film must be further increased. When working with dimensions below 0.35 microns, however, higher doping levels of boron and phosphorus in the doped film fail to achieve the desired results, and CMP processes must be used on these layers in addition to reflow to fully planarize the substrate surface.
Planarization methods have been developed using a linear track polisher. An example of a linear track polisher is that which is manufactured by OnTrak Systems, Incorporated, of Milpitas, Calif. FIG. 3 shows an example of such an apparatus. Linear track polisher 30 includes a substrate polishing head assembly 32, a continuous belt having a continuous polishing surface 34 thereon, and a chemical mixture feed assembly 36. Continuous polishing surface 34 is typically composed of a soft material such as polyurethane, similar to a typical polishing pad on a rotational polisher. The continuous belt of a linear track polisher may be less rigid than a typical polishing pad on a rotational polisher, such as rotational polisher 11 in FIG. 1. The speeds of the continuous belt which linear track polishers are capable of achieving, however, tend to compensate for the lack of rigidity of the continuous belt.
A constant downward pressure is applied to the substrate polishing head assembly 32, holding a semiconductor substrate 10 against continuous polishing surface 34. Belt drive motors drive two belt drums 38 which cause continuous polishing surface 34 to move in the direction as indicated by arrows seen in FIG. 3. Continuous polishing surface 34 may consist of a polyurethane type material. The chemical mixture feed assembly 36 delivers a liquid or aqueous mixture to the region where semiconductor substrate 10 makes contact with continuous polishing surface 34. The liquid or aqueous mixture is typically a colloidal slurry with abrasive characteristics suitable for the specific type of material being removed. In another embodiment, continuous polishing surface 34 may also contain fixed abrasives incorporated into a resin material. In the case of this other embodiment of continuous polishing surface 34, the liquid or aqueous mixture need not have abrasive characteristics.
While the linear track polisher has shown potential for improving the rate of material removal during a CMP operation on a semiconductor substrate, thereby improving the rate at which semiconductor substrate can be processed, advancements are needed to simplify the processing and improve the results obtained. In the case of both rotational polishers and linear track polishers, advancements are needed to reduce unacceptable variations in semiconductor substrate thickness in order to accommodate the trend towards increasing the overall size of semiconductor substrates by holding to necessary tolerances across the entire semiconductor substrate.
A novel method for the planarization of a semiconductor substrate is disclosed herein. The novel method can be performed on different polishing apparatus in which a continuous polishing surface polishes a front planar surface of a semiconductor substrate. The polishing apparatus can be either a rotational polisher or a linear track polisher. In a rotational polisher, the continuous polishing surface is situated on a polishing pad that rotates relative to the front planar surface of the semiconductor substrate. In a linear track polisher, there is a substrate polishing head assembly in which the semiconductor substrate is affixed so that the planar surface of the semiconductor substrate forms a polishing interface with a continuous polishing surface situated upon a continuous or endless belt.
In summary, the novel method includes the steps of applying a first polishing pressure to the substrate polishing head assembly against the continuous polishing surface, the continuous polishing surface moving at a first polishing speed for a first selected time, with a first liquid or aqueous mixture applied to a region between the substrate polishing head assembly and the continuous polishing surface on the front planar surface of the semiconductor substrate. Next, a second polishing pressure is applied to the substrate polishing head assembly against the same continuous polishing surface, the continuous polishing surface moving at a second polishing speed for a second selected time, with a second liquid or aqueous mixture applied to region between the substrate polishing head assembly and the continuous polishing surface on the front planar surface of the semiconductor substrate, wherein the second polishing pressure is less than the first polishing pressure and the second polishing speed is less than the first polishing speed.
As a further aspect to the novel method disclosed herein a third polishing pressure at a third polishing speed for a third selected time can be effected, wherein a third liquid or aqueous mixture is applied to a region between the substrate polishing head assembly and the continuous polishing surface on the front planar surface of the semiconductor substrate, wherein the third liquid or aqueous mixture contains no abrasive or colloidal elements. In this step, the third pressure and speed are less than, respectively, the first and second pressures and speeds.